A high-speed hybrid Full Adder with low power consumption
نویسندگان
چکیده
منابع مشابه
Design of Low Power High Speed Hybrid Full Adder
In this paper, a proposed 1-bit hybrid full adder design employing both transmission gate logic and complementary metal– oxide–semiconductor (CMOS) logic is reported. The design is implemented for 1-bit Ripple Carry Adder and then is extended for 64-bit Ripple Carry Adder. The circuit is implemented using Mentor Graphics tools 130nm technology. The performance parameters such as delay, area, to...
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In the recent year, many other new circuits are proposed using less number of transistors with less delay and extremely low power requirement. An adder consisting with less transistors don't give full swing outputs for all input combinations and there is difference in output level for various combinations and these circuits have very low driving capabilities. other circuits also are proposed in...
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In digital CMOS design, power consumption has been a major concern for several years advanced IC fabrication technology allows the use of nano-scale devices so inability to get power to circuits, power leakage or to remove the heat they generate. By optimizing the transistor size in each stage power and delay can be minimized. This paper presents the analysis of full adders having efficient par...
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2012
ISSN: 1349-2543
DOI: 10.1587/elex.9.1900